**Commenced**in January 2007

**Frequency:**Monthly

**Edition:**International

**Paper Count:**101

# Search results for: Arithmetic

##### 101 Two Different Computing Methods of the Smith Arithmetic Determinant

**Authors:**
Xing-Jian Li,
Shen Qu

**Abstract:**

The Smith arithmetic determinant is investigated in this paper. By using two different methods, we derive the explicit formula for the Smith arithmetic determinant.

**Keywords:**
Elementary row transformation,
Euler function,
Matrix decomposition,
Smith arithmetic determinant.

##### 100 A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic

**Authors:**
Yukinari Minagi ,
Akinori Kanasugi

**Abstract:**

**Keywords:**
dynamic reconfiguration,
floating-point arithmetic,
double precision,
FPGA

##### 99 On Some Properties of Interval Matrices

**Authors:**
K. Ganesan

**Abstract:**

**Keywords:**
Interval arithmetic,
Interval matrix,
linear equations.

##### 98 A Dynamically Reconfigurable Arithmetic Circuit for Complex Number and Double Precision Number

**Authors:**
Haruo Shimada,
Akinori Kanasugi

**Abstract:**

**Keywords:**
arithmetic circuit,
complex number,
double precision,
dynamic reconfiguration

##### 97 A Reduced-Bit Multiplication Algorithm for Digital Arithmetic

**Authors:**
Harpreet Singh Dhillon,
Abhijit Mitra

**Abstract:**

A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.

**Keywords:**
Multiplication,
algorithm,
Vedic mathematics,
digital
arithmetic,
reduced-bit.

##### 96 Membership Surface and Arithmetic Operations of Imprecise Matrix

**Authors:**
Dhruba Das

**Abstract:**

**Keywords:**
Imprecise number,
Imprecise vector,
Membership
surface,
Imprecise matrix.

##### 95 Implementation and Analysis of Elliptic Curve Cryptosystems over Polynomial basis and ONB

**Authors:**
Yong-Je Choi,
Moo-Seop Kim,
Hang-Rok Lee,
Ho-Won Kim

**Abstract:**

**Keywords:**
Elliptic Curve Cryptosystem,
Crypto Algorithm,
Polynomial Basis,
Optimal Normal Basis,
Security.

##### 94 OWA Operators in Generalized Distances

**Authors:**
José M. Merigó,
Anna M. Gil-Lafuente

**Abstract:**

**Keywords:**
Aggregation operators,
Distance measures,
Quasi- OWA operator.

##### 93 An Algorithm Proposed for FIR Filter Coefficients Representation

**Authors:**
Mohamed Al Mahdi Eshtawie,
Masuri Bin Othman

**Abstract:**

Finite impulse response (FIR) filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors, and efficient implementation. In contrast, they have a major disadvantage of high order need (more coefficients) than IIR counterpart with comparable performance. The high order demand imposes more hardware requirements, arithmetic operations, area usage, and power consumption when designing and fabricating the filter. Therefore, minimizing or reducing these parameters, is a major goal or target in digital filter design task. This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response. With this algorithm, the FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients. Therefore, reducing the arithmetic complexity needed to get the filter output. Consequently, the system characteristic i.e. power consumption, area usage, and processing time are also reduced. The proposed algorithm is more powerful when integrated with multiplierless algorithms such as distributed arithmetic (DA) in designing high order digital FIR filters. Here the DA usage eliminates the need for multipliers when implementing the multiply and accumulate unit (MAC) and the proposed algorithm will reduce the number of adders and addition operations needed through the minimization of the non-zero values coefficients to get the filter output.

**Keywords:**
Pulse shaping Filter,
Distributed Arithmetic,
Optimization algorithm.

##### 92 Autonomous Vehicle Navigation Using Harmonic Functions via Modified Arithmetic Mean Iterative Method

**Authors:**
Azali Saudi,
Jumat Sulaiman

**Abstract:**

**Keywords:**
Modified Arithmetic Mean method,
Harmonic
functions,
Laplace’s equation,
path planning.

##### 91 Stepsize Control of the Finite Difference Method for Solving Ordinary Differential Equations

**Authors:**
Davod Khojasteh Salkuyeh

**Abstract:**

An important task in solving second order linear ordinary differential equations by the finite difference is to choose a suitable stepsize h. In this paper, by using the stochastic arithmetic, the CESTAC method and the CADNA library we present a procedure to estimate the optimal stepsize hopt, the stepsize which minimizes the global error consisting of truncation and round-off error.

**Keywords:**
Ordinary differential equations,
optimal stepsize,
error,
stochastic arithmetic,
CESTAC,
CADNA.

##### 90 Relational Framework and its Applications

**Authors:**
Lidia Obojska

**Abstract:**

**Keywords:**
language,
unary relations,
arithmetic,
computability

##### 89 New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

**Authors:**
Shiv Shankar Mishra,
S. Wairya,
R. K. Nagaria,
S. Tiwari

**Abstract:**

**Keywords:**
Exclusive-OR (XOR),
Exclusive-NOR (XNOR),
High speed,
Low power,
Arithmetic Circuits.

##### 88 A Robust Redundant Residue Representation in Residue Number System with Moduli Set(rn-2,rn-1,rn)

**Authors:**
Hossein Khademolhosseini,
Mehdi Hosseinzadeh

**Abstract:**

**Keywords:**
Binary to RNS converter,
Carry save adder,
Computer arithmetic,
Residue number system.

##### 87 Research of Ring MEMS Rate Integrating Gyroscopes

**Authors:**
Hui Liu,
Haiyang Quan

**Abstract:**

**Keywords:**
Rate gyroscope,
Rate integrating gyroscope,
Whole
angle mode,
MATLAB modeling,
DSP control.

##### 86 Compensated CIC-Hybrid Signed Digit Decimation Filter

**Authors:**
Vishal Awasthi,
Krishna Raj

**Abstract:**

In this paper, firstly, we present the mathematical modeling of finite impulse response (FIR) filter and Cascaded Integrator Comb (CIC) filter for sampling rate reduction and then an extension of Canonical signed digit (CSD) based efficient structure is presented in framework using hybrid signed digit (HSD) arithmetic. CSD representation imposed a restriction that two non-zero CSD coefficient bits cannot acquire adjacent bit positions and therefore, represented structure is not economical in terms of speed, area and power consumption. The HSD based structure gives optimum performance in terms of area and speed with 37.02% passband droop compensation.

**Keywords:**
Multirate filtering,
compensation theory,
CIC filter,
compensation filter,
signed digit arithmetic,
canonical signed digit.

##### 85 Efficient Power-Delay Product Modulo 2n+1 Adder Design

**Authors:**
Yavar Safaei Mehrabani,
Mehdi Hosseinzadeh

**Abstract:**

As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.

**Keywords:**
Computer arithmetic,
modulo 2n+1 adders,
Residue Number System (RNS),
VLSI.

##### 84 A PN Sequence Generator based on Residue Arithmetic for Multi-User DS-CDMA Applications

**Authors:**
Chithra R,
Pallab Maji,
Sarat Kumar Patra,
Girija Sankar Rath

**Abstract:**

**Keywords:**
Direct-Sequence Code Division Multiple Access (DSCDMA),
Multiple-Access Interference (MAI),
PN Sequence,
Residue
Number System (RNS).

##### 83 A New Block-based NLMS Algorithm and Its Realization in Block Floating Point Format

**Authors:**
Abhijit Mitra

**Abstract:**

we propose a new normalized LMS (NLMS) algorithm, which gives satisfactory performance in certain applications in comaprison with con-ventional NLMS recursion. This new algorithm can be treated as a block based simplification of NLMS algorithm with significantly reduced number of multi¬ply and accumulate as well as division operations. It is also shown that such a recursion can be easily implemented in block floating point (BFP) arithmetic, treating the implementational issues much efficiently. In particular, the core challenges of a BFP realization to such adaptive filters are mainly considered in this regard. A global upper bound on the step size control parameter of the new algorithm due to BFP implementation is also proposed to prevent overflow in filtering as well as weight updating operations jointly.

**Keywords:**
Adaptive algorithm,
Block floating point arithmetic,
Implementation issues,
Normalized least mean square methods

##### 82 A New Reliability Allocation Method Based On Fuzzy Numbers

**Authors:**
Peng Li,
Chuanri Li,
Tao Li

**Abstract:**

Reliability allocation is quite important during early design and development stages for a system to apportion its specified reliability goal to subsystems. This paper improves the reliability fuzzy allocation method, and gives concrete processes on determining the factor and sub-factor sets, weight sets, judgment set, and multi-stage fuzzy evaluation. To determine the weight of factor and sub-factor sets, the modified trapezoidal numbers are proposed to reduce errors caused by subjective factors. To decrease the fuzziness in fuzzy division, an approximation method based on linear programming is employed. To compute the explicit values of fuzzy numbers, centroid method of defuzzification is considered. An example is provided to illustrate the application of the proposed reliability allocation method based on fuzzy arithmetic.

**Keywords:**
Reliability allocation,
fuzzy arithmetic,
allocation
weight.

##### 81 Extended Arithmetic Precision in Meshfree Calculations

**Authors:**
Edward J. Kansa,
Pavel Holoborodko

**Abstract:**

Continuously differentiable radial basis functions (RBFs) are meshfree, converge faster as the dimensionality increases, and is theoretically spectrally convergent. When implemented on current single and double precision computers, such RBFs can suffer from ill-conditioning because the systems of equations needed to be solved to find the expansion coefficients are full. However, the Advanpix extended precision software package allows computer mathematics to resemble asymptotically ideal Platonic mathematics. Additionally, full systems with extended precision execute faster graphical processors units and field-programmable gate arrays because no branching is needed. Sparse equation systems are fast for iterative solvers in a very limited number of cases.

**Keywords:**
Meshless spectrally convergent,
partial differential equations,
extended arithmetic precision,
no branching.

##### 80 Reliability Evaluation using Triangular Intuitionistic Fuzzy Numbers Arithmetic Operations

**Authors:**
G. S. Mahapatra,
T. K. Roy

**Abstract:**

**Keywords:**
Fuzzy set,
Intuitionistic fuzzy number,
Systemreliability,
Triangular intuitionistic fuzzy number.

##### 79 Computationally Efficient Signal Quality Improvement Method for VoIP System

**Authors:**
H. P. Singh,
S. Singh

**Abstract:**

The voice signal in Voice over Internet protocol (VoIP) system is processed through the best effort policy based IP network, which leads to the network degradations including delay, packet loss jitter. The work in this paper presents the implementation of finite impulse response (FIR) filter for voice quality improvement in the VoIP system through distributed arithmetic (DA) algorithm. The VoIP simulations are conducted with AMR-NB 6.70 kbps and G.729a speech coders at different packet loss rates and the performance of the enhanced VoIP signal is evaluated using the perceptual evaluation of speech quality (PESQ) measurement for narrowband signal. The results show reduction in the computational complexity in the system and significant improvement in the quality of the VoIP voice signal.

**Keywords:**
VoIP,
Signal Quality,
Distributed Arithmetic,
Packet Loss,
Speech Coder.

##### 78 Accelerating Integer Neural Networks On Low Cost DSPs

**Authors:**
Thomas Behan,
Zaiyi Liao,
Lian Zhao,
Chunting Yang

**Abstract:**

**Keywords:**
Digital Signal Processor (DSP),
Integer Neural Network(INN),
Low Cost Neural Network,
Integer Neural Network DSPImplementation.

##### 77 A Novel Multiple Valued Logic OHRNS Modulo rn Adder Circuit

**Authors:**
Mehdi Hosseinzadeh,
Somayyeh Jafarali Jassbi,
Keivan Navi

**Abstract:**

Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m^{2} . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.

**Keywords:**
Computer Arithmetic,
Residue Number System,
Multiple Valued Logic,
One-Hot,
VLSI.

##### 76 Design and Implementation of Reed Solomon Encoder on FPGA

**Authors:**
Amandeep Singh,
Mandeep Kaur

**Abstract:**

Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FPGA Spartan II.

**Keywords:**
Galois Field,
Generator polynomial,
LFSR,
Reed Solomon.

##### 75 Products in Early Development Phases: Ecological Classification and Evaluation Using an Interval Arithmetic Based Calculation Approach

**Authors:**
Helen L. Hein,
Joachim Schwarte

**Abstract:**

As a pillar of sustainable development, ecology has become an important milestone in research community, especially due to global challenges like climate change. The ecological performance of products can be scientifically conducted with life cycle assessments. In the construction sector, significant amounts of CO_{2} emissions are assigned to the energy used for building heating purposes. Therefore, sustainable construction materials for insulating purposes are substantial, whereby aerogels have been explored intensively in the last years due to their low thermal conductivity. Therefore, the WALL-ACE project aims to develop an aerogel-based thermal insulating plaster that would achieve minor thermal conductivities. But as in the early stage of development phases, a lot of information is still missing or not yet accessible, the ecological performance of innovative products bases increasingly on uncertain data that can lead to significant deviations in the results. To be able to predict realistically how meaningful the results are and how viable the developed products may be with regard to their corresponding respective market, these deviations however have to be considered. Therefore, a classification method is presented in this study, which may allow comparing the ecological performance of modern products with already established and competitive materials. In order to achieve this, an alternative calculation method was used that allows computing with lower and upper bounds to consider all possible values without precise data. The life cycle analysis of the considered products was conducted with an interval arithmetic based calculation method. The results lead to the conclusion that the interval solutions describing the possible environmental impacts are so wide that the result usability is limited. Nevertheless, a further optimization in reducing environmental impacts of aerogels seems to be needed to become more competitive in the future.

**Keywords:**
Aerogel-based,
insulating material,
early develop¬ment phase,
interval arithmetic.

##### 74 Efficient Semi-Systolic Finite Field Multiplier Using Redundant Basis

**Authors:**
Hyun-Ho Lee,
Kee-Won Kim

**Abstract:**

**Keywords:**
Finite field,
Montgomery multiplication,
systolic array,
cryptography.

##### 73 A New Approach to Design an Efficient CIC Decimator Using Signed Digit Arithmetic

**Authors:**
Vishal Awasthi,
Krishna Raj

**Abstract:**

Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.

**Keywords:**
Sampling rate conversion,
Multirate Filtering,
Compensation Theory,
Decimation filter,
CIC filter,
Redundant signed digit arithmetic,
Fast adders.

##### 72 Simulation Based VLSI Implementation of Fast Efficient Lossless Image Compression System Using Adjusted Binary Code & Golumb Rice Code

**Authors:**
N. Muthukumaran,
R. Ravi

**Abstract:**

The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.

**Keywords:**
Image compression,
Pixel,
Compression Ratio,
Adjusted Binary code,
Golumb Rice code,
High Definition display,
VLSI Implementation.