Common M environment variables in kernel compilation


Main Makefile:

ifeq ("$(origin V)", "command line")






ifeq ($(KBUILD_VERBOSE),1)

  quiet =

  Q =



  Q = @


So the Q here represents whether to compile silently for quiet, which needs to be specified by passing in V=1 at make compilation time.


Pseudo target


# Declare the contents of the .PHONY variable as phony.  We keep that
# information in a variable so we can use it in if_changed and friends.

Directory definition

First, in the main Makefile:

 objtree     := .

 src     := $(srctree)

 obj     := $(objtree)


 VPATH       := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD))


 export srctree objtree VPATH

Some environment variables are defined in the main Makefile, and srctree / objtree will be exported. These two environment variables are unchanged in the whole process of kernel compilation, and the environment variable (obj) needs special attention,

It will change during the compilation of each subdirectory. The process of change is as follows:



# Shorthand for $(Q)$(MAKE) -f scripts/ obj=

# Usage:

# $(Q)$(MAKE) $(build)=dir

build := -f $(srctree)/scripts/ obj


# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=

# Usage:

# $(Q)$(MAKE) $(modbuiltin)=dir

modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj


# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.dtbinst obj=

# Usage:

# $(Q)$(MAKE) $(dtbinst)=dir

dtbinst := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.dtbinst obj


# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=

# Usage:

# $(Q)$(MAKE) $(clean)=dir

clean := -f $(srctree)/scripts/Makefile.clean obj


# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.headersinst obj=

# Usage:

# $(Q)$(MAKE) $(hdr-inst)=dir

hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj

A series of makefile environment variables are defined in kbuild.include, and all of them contain the word obj. That is to say, in the subsequent Makefile, the corresponding obj=xxx environment variables will be passed to each subdirectory during compilation.

For example, in the main Makefile:

 %.s: %.c prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.i: %.c prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.o: %.c prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.lst: %.c prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.s: %.S prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.o: %.S prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.symtypes: %.c prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

 %.ll: %.c prepare scripts FORCE

     $(Q)$(MAKE) $(build)=$(build-dir) $(target-dir)$(notdir $@)

Here, $(build) = $(build DIR) will be called so that the value of $(obj) will be updated to the compilation process of each sub module.

Keywords: Makefile

Added by San_John on Sun, 29 Dec 2019 17:11:03 +0200