HDMI Fundamentals

1, Principle

HDMI Adopt and DVI Same transmission principle-TMDS(Transition Minimized Differential signal)，That is, the transmission differential signal is minimized.
TMDS The transmission system is divided into: sending end; Receiver.
Sender:( RGB 24 bit parallel data of the signal, R，G，B 8 for each of the three primary colors bit code;-->  code --> Parallel serial conversion --> Independent channel transmission)

Receiving end: (decoding -- > serial parallel conversion -- > display control end (receive clock signal at the same time to realize synchronization))

2, TMDS

each TMDS Links include: 3 RGB Signal data channel and 1 clock signal channel.
8 Bit video and audio signals are converted into 10 bit data with minimum transmission and DC balance.
The minimum loop transmission differential signal is converted through exclusive or and exclusive or non logic algorithms. The first 8 bits are obtained by original signal operation, the ninth bit indicates the operation mode, and the tenth bit corresponds to DC balance.
In general, HDMI The transmitted coding format shall include video data, control data and data packet (the data packet includes audio data and additional information data, such as error correction code, etc.). HDMI The information transmission process can be divided into the above three data transmission stages.

3, Video timing standard

HDMI The scanning mode of the display starts from a point in the upper left corner of the screen and from left to the starting position of the next line on the left side of the screen. During this period, CRT Blanking the electron beam and synchronizing with the line synchronization signal at the end of each line; When all lines are scanned, a frame is formed. The field synchronization signal is used for field synchronization, and the scanning returns to the upper left of the screen. At the same time, the field blanking is carried out to start the next frame.
The time to complete one line scanning is called horizontal scanning time, and its corresponding frequency is called line rate; The time to complete a frame (whole screen) scanning is called the vertical scanning time, and its corresponding frequency is called the field frequency, that is, the frequency of refreshing a screen, which is 60 Hz And 75 Hz，Standard display field frequency 60 Hz. 
Clock frequency: 1024 x768@59.94Hz(60Hz)，Each field corresponds to 806 line cycles, of which 768 are display lines, and each display line includes 1344 clock points,1024 is the effective display area, which shows that the point frequency 806 is required*1344*60 About 65 MHz. 

FPGA program

The following discusses the development of HDMI Demo program of FPGA.

1, TOP level code

FPGA top-level code includes:

• The clock PLL is used to generate HDMI video point frequency.
• I2C Master is used to configure HDMI chip.
• HDMI input data and generate HDMI frame data packet.

2, Clock

PLL Generate 148.5MHz The corresponding display resolution is 1920*1080，The line cycle is 1125 lines, and the corresponding point of each line is 2200 pix. 1125*2200*60=148.5MHz. 

3, Configuring HDMI with I2C Master

device address: 0x72
register address: 0x08
write data: 0x35

device address: 0x7a
register address: 0x2f
write data: 0x00

4, HDMI frame packet generation module

1. Interface

• Video CLK
• Video horizon Sync
• Video vertical Sync
• Video DE signal
• Video RGB data

2. Line scanning sequence

Front Porch + Sync + Back Porch + Active Video

3. Field scanning sequence

Front Porch + Sync + Back Porch + Active Video

4. Code fragment analysis

//1920x1080 148.5Mhz
`ifdef  VIDEO_1920_1080
parameter H_ACTIVE = 16'd1920;
parameter H_FP = 16'd88;
parameter H_SYNC = 16'd44;
parameter H_BP = 16'd148; 
parameter V_ACTIVE = 16'd1080;
parameter V_FP  = 16'd4;
parameter V_SYNC  = 16'd5;
parameter V_BP  = 16'd36;
...
`endif

parameter H_TOTAL = H_ACTIVE + H_FP + H_SYNC + H_BP;//horizontal total time (pixels)
parameter V_TOTAL = V_ACTIVE + V_FP + V_SYNC + V_BP;//vertical total time (lines)

This code is used to define the clock cycle of line scanning and field scanning at different resolutions.

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        h_cnt <= 12'd0;
    else if(h_cnt == H_TOTAL - 1)//horizontal counter maximum value
        h_cnt <= 12'd0;
    else
        h_cnt <= h_cnt + 12'd1;
end

This code defines a counter for line scanning.

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        v_cnt <= 12'd0;
    else if(h_cnt == H_FP  - 1)//horizontal sync time
        if(v_cnt == V_TOTAL - 1)//vertical counter maximum value
            v_cnt <= 12'd0;
        else
            v_cnt <= v_cnt + 12'd1;
    else
        v_cnt <= v_cnt;
end

This code defines a counter for field scanning (vertical direction).

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        active_x <= 12'd0;
    else if(h_cnt >= H_FP + H_SYNC + H_BP - 1)//horizontal video active
        active_x <= h_cnt - (H_FP[11:0] + H_SYNC[11:0] + H_BP[11:0] - 12'd1);
    else
        active_x <= active_x;
end

active_x records the position of the currently scanned line, i.e. x position, in pixel.

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        hs_reg <= 1'b0;
    else if(h_cnt == H_FP - 1)//horizontal sync begin
        hs_reg <= HS_POL;
    else if(h_cnt == H_FP + H_SYNC - 1)//horizontal sync end
        hs_reg <= ~hs_reg;
    else
        hs_reg <= hs_reg;
end

hs_reg gives the SYNC signal of line scanning.

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        h_active <= 1'b0;
    else if(h_cnt == H_FP + H_SYNC + H_BP - 1)//horizontal active begin
        h_active <= 1'b1;
    else if(h_cnt == H_TOTAL - 1)//horizontal active end
        h_active <= 1'b0;
    else
        h_active <= h_active;
end

h_active gives the active Video signal of line scanning.

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        vs_reg <= 1'd0;
    else if((v_cnt == V_FP - 1) && (h_cnt == H_FP - 1))//vertical sync begin
        vs_reg <= HS_POL;
    else if((v_cnt == V_FP + V_SYNC - 1) && (h_cnt == H_FP - 1))//vertical sync end
        vs_reg <= ~vs_reg;  
    else
        vs_reg <= vs_reg;
end

always@(posedge clk or posedge rst)
begin
    if(rst == 1'b1)
        v_active <= 1'd0;
    else if((v_cnt == V_FP + V_SYNC + V_BP - 1) && (h_cnt == H_FP - 1))//vertical active begin
        v_active <= 1'b1;
    else if((v_cnt == V_TOTAL - 1) && (h_cnt == H_FP - 1)) //vertical active end
        v_active <= 1'b0;   
    else
        v_active <= v_active;
end

The above codes generate SYNC signal and active video signal of field scanning respectively.

assign video_active = h_active & v_active;

video_ The active signal is the identification that both line scanning and field scanning enter the effective display timing.

else if(video_active)
        if(active_x == 12'd0)
            begin
                rgb_r_reg <= WHITE_R;
                rgb_g_reg <= WHITE_G;
                rgb_b_reg <= WHITE_B;
            end
        else if(active_x == (H_ACTIVE/8) * 1)
            begin
                rgb_r_reg <= YELLOW_R;
                rgb_g_reg <= YELLOW_G;
                rgb_b_reg <= YELLOW_B;
            end         

The above code fragment gives specific RGB data according to the position of the x-axis when both line scanning and field scanning enter the effective display timing.

assign de = video_active_d0;

The DE signal is an active video signal, delaying one clock cycle, which should be the condition judgment of using the active video signal when outputting RGB data. Therefore, the output RGB data is originally delayed by one clock cycle relative to the active video signal, so the output DE signal also needs to be delayed by one clock cycle.

5. Output signal

The output signals are:

• video clk: 148.5MHz
• Horizontal scan SYNC signal
• Field scan SYNC signal
• DE signal
• RGB data