code
module alu(a,b,aluc,r,z);
input [31:0] a
input [31:0] b;
input [3:0] aluc;
output [31:0] r;
output z;
assign r = cal (a,b,aluc);
assign z =~|r;
function [31:0] cal;
input [31:0] a,b;
input [3:0] aluc;
casex (aluc)
//0 4 1 5 2 6 3 7 F
4'bx000: cal =a + b;
4'bx100: cal =a - b;
4'bx001: cal =a & b;
4'bx101: cal =a | b;
4'bx010: cal =a ^ b;
4'bx110: cal ={b[15:0],16'h0};
4'bx011: cal =b << a[4:0];
4'b0111: cal =b >> a[4:0];
4'b1111: cal =$signed(b) >>> a[4:0];
endcase
endfunction
endmodule
module shift (d,sa,right,arith,sh);
input [31:0] d;
input [4:0] sa;
input right,arith;
output [31:0] sh;
reg [31:0] sh;
always @* begin
if (right == 0) begin // shift left
sh = d << sa;
end else if (arith == 0) begin // shift right logical
sh = d >> sa;
end else begin // shift right arithmetic
sh = $signed(d) >>> sa;
end
end
endmodule
module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);
input [4:0] rna,rnb,wn;
input [31:0] d;
input we,clk,clrn;
output [31:0] qa,qb;
reg [31:0] register [1:31];
assign qa = (rna == 0) ? 0 : register[rna];
assign qb = (rnb == 0) ? 0 : register[rnb];
//posedge: upper edge, negedge: lower edge
always @ (posedge clk or negedge clrn) begin
if (clrn == 0) begin //Initialize register file
integer i;
for (i=1; i<32; i=i+1)
register[i] <= 0; //< = non blocking assignment
end else begin
if ((wn != 0) && (we == 1)) //we: write enable, wn: write number
register[wn] <= d; //< = non blocking assignment
end
end
endmodule
Short answer
Draw the structure diagram of von Neumann computer
In the main memory of the computer, a certain ROM area is usually set, and ROM and RAM are uniformly addressed. Please indicate the purpose of setting the ROM area.
Store boot data
The word length of a computer is 32b, of which the address code length is 22b. If the main memory is addressed by word, what is the maximum capacity of the main memory (word)? If main memory is addressed by bytes, what is the maximum capacity of main memory (bytes)?
2^22=4M word 32/8 * 2^22=16MB
Why should computers adopt multi-level storage systems?
People always hope that the memory has the characteristics of large capacity, fast speed and low cost. In fact, the fast memory has high cost and small capacity, and the memory with large capacity and low cost is relatively slow. In order to solve the contradiction between memory capacity, speed and price, it is necessary to build a multi-level storage system.
What principle is the establishment of multi-level storage system based on? Briefly describe this principle.
Principle of program locality; Program locality means that the program presents a local law during execution, that is, in a period of time, CPU When accessing memory, whether accessing instructions or data, the accessed units tend to be concentrated in a small continuous area
Try to describe the characteristics of volatile memory and nonvolatile memory, and give two examples respectively.
Volatile memory: loss of information after power failure: SRAM,DRAM Nonvolatile memory: no loss of information after power failure: disk ROM
What is memory bandwidth? If the data bus width of the memory is 32 bits and the access cycle is 200ns, what is the memory bandwidth?
The bandwidth of memory refers to the maximum amount of information in and out of memory per unit time. Memory bandwidth = 1/200ns ×32 position = 160M position / second = 20MB/ second = 5M word / Second attention :Word length 32 bits,Not 16 bits.(notes: 1ns=10^-9s )
< > Level 3 storage system can be divided into two levels: cache main memory and main memory auxiliary memory. Please compare these two levels
| Cache - main memory | Main memory - auxiliary memory | |
|---|---|---|
| objective | Address storage system speed issues | Resolve storage system capacity issues |
| Based on the basic principles of | Program locality principle | Program locality principle |
| storage capacity | Small | large |
| Reading and writing speed | fast | slow |
| Implementation method | Hardware | Software |
Instructions and data are stored in memory. How can a computer distinguish them
Instructions and data are distinguished by different time periods, that is, what is taken out in the instruction fetch stage is instructions, and what is taken out in the instruction execution stage is data. Distinguished by address source PC The fetching that provides the storage unit address is the instruction, and the fetching that provides the storage unit address by the instruction address code part is the operand.
< > does the CPU respond to DMA requests and interrupt requests at the same time? Why?
Different, because the exchange speeds of the two methods are very different, so CPU You must query and respond at shorter intervals DMA Request.
What are multiple interrupts? What are the necessary conditions for implementing multiple interrupts
Multiple interrupts are when CPU During the execution of an interrupt service program, a higher-level and more urgent event occurs, CPU The process of suspending the execution of the current interrupt service program, transferring to deal with the interrupt of the event, and returning to the current interrupt service program to continue the execution. The necessary condition for realizing multiple interrupts is that during the current interrupt service period, the interrupt allowable trigger is 1, that is, open interrupt.
< > What are the two general location methods for main memory? Briefly describe its characteristics
(1 One dimensional address decoding method There is only one address decoder. Word selection selects all bits of a word. All bits of each row in the storage array correspond to one word,Share a word selection line; Each column corresponds to the same bit of different words,And connected with a common bit line. The address code only needs to be decoded once to select the storage unit. The longer the number of address code bits, the more complex the decoder structure and the higher the cost. Therefore, this addressing method is suitable for memory chips with faster speed and smaller capacity. (2)Two dimensional address decoding method The storage units in the memory are arranged in an array need X and Y Two address decoders, X Called a line decoder, Y It is called column decoder. only X Decoder and Y The storage unit at the intersection of rows and columns selected by the decoder at the same time is selected, which is mainly used for high-capacity memory structure
What role can Cache play in the memory hierarchy?
solve CPU It solves the contradiction between main memory speed and price
What is interrupt priority? What is the meaning of interrupt nesting
The so-called interrupt priority refers to when two or more interrupt sources apply for interrupt at the same time,The system will give priority to the interrupt source with high priority. Interrupt nesting refers to the process of interrupt execution,If a higher priority interrupt source sends an interrupt request,The system interrupts the executing interrupt and processes the interrupt events of higher priority interrupt sources.
What is an I/O interface? Why do I/O interfaces need to be set in the computer system? What role will they play
IO Interface refers to the interface logic that connects the host with external devices or other external systems in the computer IO The interface is the bridge between the host and peripherals. The information exchange between the host and peripherals can be realized through the interface
< > describe the workflow of interrupt mode I / O control
CPU Continue to perform other operations after issuing the command to start the peripheral, When the peripheral completes the data preparation, it actively applies to the host for interruption,request CPU Data processing, CPU After responding to the interrupt, complete the data transmission by executing the interrupt service program of the device
Briefly describe the execution of the following instructions: LW, R24, 100 (R15)
According to program counter, Take the instruction from the memory and PC + 4 Decode the instruction and read the data in register 15 from the register file Calculate memory address: this data is added to the immediate number 100 Memory access: the result of addition is used as the memory address, Read data from memory Write the data to register 24
What are three types of MIPS instructions? Give an example of each instruction and explain the function of the instruction.
R,I,J
add rd,rs,rt Put register rs and rt The contents are added, and the result exists in the register rd in
add rt,rs,imm Put register rs Data and unsigned immediate imm Add and store the results in rt in
--------
ADD $8,$9,$10 -> $8<=($9)+($10)
ADDI $t8,$s3,100 -> $8=($9)+100
J address -> PC={PC[31:28]+address<<2}
What types of instructions should a more complete instruction system include?
Data processing, data storage, data transmission, program control
< > compare DMA mode with program interrupt mode from the following five aspects.
| Program interrupt mode | DMA mode | |
|---|---|---|
| data transfer | Program (software) | Hardware |
| response time | slow | fast |
| Handling exceptions | can | No |
| Interrupt request | Transmit data | End of processing |
| priority | low | high |
What are the three MIPS CPU instruction formats? Try to write their instruction formats respectively.
R Type instruction:|Opcode|rs|rt|rd|Shamt|Funct| I Type instruction:|Opcode|rs|rt|immediate| J Type instruction:|Opcode|JumpAddr| (Bit order: 31-0)
< > What are the addressing modes of MIPs instructions? Try to illustrate with examples.
MIPS Most instructions of the processor are addressed in sequence. There are three addressing modes involved in program transfer:
1. Relative addressing
BEQ rs,rt,label
BEQ $t1,$t2,label，When $t1=$t2 The instruction transfer address is PC=PC+label
2. register indirect addressing
JALR $1,$3 take PC+4 Save values to $1 , and then execute PC=$s3
3. pseudodirect addressing
J label When the instruction is executed, the 32-bit transfer address is PC High 4-bit and 26 bit JumpAddr It is composed of two bits spliced to the left, PC={PC[31:28]，label<<2}
Try to explain the functions of the following instructions and write the corresponding 32-bit MIPS CPU binary machine instruction code.
(1)sll r13, r12, 25 ; (2)addi r3, r1, -1 ; (3) lui r29, 0xffff ;
Shamt: Shift Amount
1. sll rd,rt,shamt
r13=r12<<25
000000 00000 01100 01101 11001 000000
2. addi rt,rs,imm
rt<-(rs)+imm
001000 00001 00011 1111111111111
3. lui rt,imm
rt <- immediate<<16 ；Put the 16 bit immediate number 16 higher than the destination register
Bit, the lower 16 bits of the target register are filled with 0
001111 00000 11101 1111111111111111
Comprehensive questions
The machine word length is 32 bits, the main memory capacity is 1MB, 16 general registers, and a total of 32 instructions. Please design a double address instruction format, which requires six addressing modes: immediate, direct, register, register indirect, index and relative.
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The word length of a machine is 32 bits, the main memory capacity is 2M*32 bits, the single word length instruction, and the storage word length is equal to the instruction word length. There are 168 operations, the number of operation code bits is fixed, and register addressing, register indirect addressing, immediate addressing, direct addressing and indirect addressing are adopted. There are 32 32-bit general-purpose registers in the CPU. Test answer:
- Design the three address instruction, draw the three address instruction format and point out the function of each field;
- The maximum range of direct addressing of the instruction;
- Register indirect addressing range;
- Range of immediate (signed machine number represented by complement) (expressed in decimal)
> Handwritten, right or wrong < 1. |OP |X |rs |rt |rd |D | |8 |3 |5 |5 |5 |6 | OP: Operation code X: Addressing mode rs: Source register address rt: Another source register address rd: Destination register address D: Use for immediate and indirect addressing 2. 2^6-1 3. 0~2^32-1 , 4GW 4. -32 ~ 31
One with a capacity of 16K × What is the sum of address lines and data lines of 32-bit memory? How many memory chips are required when the following different specifications of memory chips are selected? 1K × 4-bit, 2K × 8-bit, 4K × 4-bit, 16K × 1 bit, 4K × 8-bit, 8K × 8 bits
Suppose that a certain machine has five interrupt sources L0, L1, L2, L3 and L4, which are sorted as L0 L1 L2 L3 L4 from high to low according to the priority of interrupt response. Now it is required to change the interrupt processing order to L1 L4 L2 L0 L3, and write the shielding word of each interrupt source according to the following format
| Interrupt source | Original shielded word (L01234) | New shielded word (L01234) |
|---|---|---|
| L0 | 11111 | 10010 |
| L1 | 01111 | 11111 |
| L2 | 00111 | 10110 |
| L3 | 00011 | 00010 |
| L4 | 00001 | 10111 |
There are 32 32-bit general registers in the CPU. An instruction system that can accommodate 64 operations is designed. Assuming that the instruction word length is equal to the machine word length, try to answer the following questions.
- If the main memory can be directly or indirectly addressed, what is the maximum storage space that can be directly addressed by using "register memory" instructions? Draw the instruction format and explain the meaning of each field.
- On the premise of meeting (1), if the general register is used as the base register, what are the characteristics of the instruction format of the above "register memory" instruction? Draw the instruction format and indicate how much storage space can be accessed by such instructions?
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The instruction format of a microcomputer is as follows:
In the format, D is the displacement, and X is the characteristic value of addressing mode:
- X=00, direct addressing;
- X=01, index with index register R1
- X=10, indexed with index register R2
- X=11, relative addressing
If (PC) = 1234H, (R1) = 0037H,(R2)=1122H,(H represents hexadecimal number), please determine the effective address of the following instruction:
(1)4420H (2) 2244H (3)1322H (4)3521H (5)6723H
1. 4420H=010001,00,00100000B X=00，Direct addressing EA=D=20H 2. 2244H=001000,10,01000100B X=10，Index register R2 Indexing EA=(R2)+ D= 3. 1322H=000100,11,00100010B X=11，Relative addressing EA=(PC)+ D 4. 3521H=001101,01,0100001B X=01，Index register R1 Indexing EA=(R1)+ D= 5. 6723H=011001,11,0100011B X=11，Relative addressing EA=(PC)+D =
sample: Correct answer:(1)5472H； (2)0038H； (3)3549H； (4)679AH. (1)8341H=(1000001101000001)2. X=11，Relative address, D=41H，Valid address E=(PC)+D=5431H+41H=5472H. (2)1438H=(0001010000111000)2X=00，Direct addressing, D=38H，Valid address E=D=0038H. (3)8134H=(1000000100110100)2X=01，Index register RXl Addressing, D=34H，Valid address E=(RXl)+D=3515H+34H=3549H. (4)6228H=(0110001000101000)2X=10，Index register RX2 Addressing, D=28H，Valid address E=(RX2)+D=6766H+34H=679AH.
The multi cycle CPU of a MIPS architecture executes a program, and the instruction distribution is as follows:
Assuming that the program consists of 100 instructions, the CPU can output 2KB data after executing the program. If the CPU clock cycle T=100ps, calculate the processor's: (1) average CPI (2) average IPS (3) basic bandwidth of data output path.
CPI: the number of clock cycles required for each instruction executed by the CPU.
IPS (Instructions per second): the number of instructions executed per second
ps: picosecond, 10^-12s
CPI=4*0.45+5*0.25+4*0.15+3*0.1+2*0.05=4.05 IPS=1/(T*CPI)= 2KB/(100/IPS)
The memory of a 32-bit MIPS computer is addressed by word, and the storage fragments are as follows:
| Memory address (hexadecimal) | Storage content (formal representation) | Register address (binary) | Register contents (decimal) |
|---|---|---|---|
| 00000000 | add rd, rs, rt | 01000 | 10 |
| 00000004 | lw rt, offset(rs) | 01001 | 20 |
| 00000008 | beq rs, rt, label | 01010 | 17 |
| 0000000C | 00000008H | 01011 | 11 |
| 00000010 | 0000000AH | 01100 | 13 |
| 00000014 | 0000000BH | 01101 | 15 |
If the decimal number corresponding to each code segment of the instruction is:
$rs=8, $rt=9, $rd=10, offset=6, label=4
Please analyze the values of relevant registers under the following three conditions:
(1) What are the contents of PC register and rd register after the add instruction is executed?
(2) What are the contents of PC register and rt register after LW instruction is executed?
(3) What is the content of the PC register after the BEQ instruction is executed?
1. rd<=(rs)+(rt)=10+20=30 (rd)=30 The instruction length is 4 Byte，PC<=PC+4 (PC)=00000004H 2. rt<=Mem[(rs)+offset] (rt)=Mem[Decimal (10)+16)]=0000000AH (PC)=00000008H 3. By 2( rt)=AH=10 (rs)==(rt) therefore PC<=(PC)+ 4 + offset<<2 (PC)=1CH
other
Clock cycle
The clock cycle, also known as the oscillation cycle, is defined as the reciprocal of the clock pulse (the clock cycle is the reciprocal of the external crystal oscillator of the single chip microcomputer, such as 12 M Its clock cycle is 1/12us)，It is the most basic and smallest time unit in the computer. In one clock cycle, CPU Complete only one basic action. Clock pulse is the basic working pulse of computer, which controls the working rhythm of computer. The higher the clock frequency, the faster the working speed. 8051 Single chip microcomputer defines a clock cycle as a beat (with P Two beats are defined as a state cycle (represented by S Indicates).
Machine cycle
In computer, the execution process of an instruction is often divided into several stages, and each stage completes a work. Each work is called a basic operation, and the time required to complete a basic operation is called the machine cycle. A machine cycle of 8051 series single chip microcomputer consists of 6 cycles S Cycle (state cycle) composition. One S cycle=2 A beat( P)，So a machine cycle of 8051 single chip microcomputer=6 State cycle=12 Clock cycles. For example, external 24 M Crystal oscillator's single chip microcomputer, his one machine cycle=12/24M Second;
Instruction cycle
The time required to execute an instruction is generally composed of several machine cycles. Different commands require different machine cycles
The reciprocal of the external crystal oscillator of the single chip microcomputer, such as the 12M crystal oscillator, whose clock cycle is 1/12us), is the most basic and smallest time unit in the computer.
In one clock cycle, the CPU only completes one basic action. Clock pulse is the basic working pulse of computer, which controls the working rhythm of computer. The higher the clock frequency, the faster the working speed.
8051 Single chip microcomputer defines a clock cycle as a beat (with P Two beats are defined as a state cycle (represented by S Indicates).
Machine cycle
In computer, the execution process of an instruction is often divided into several stages, and each stage completes a work. Each work is called a basic operation, and the time required to complete a basic operation is called the machine cycle. A machine cycle of 8051 series single chip microcomputer consists of 6 cycles S Cycle (state cycle) composition. One S cycle=2 A beat( P)，So a machine cycle of 8051 single chip microcomputer=6 State cycle=12 Clock cycles. For example, external 24 M Crystal oscillator's single chip microcomputer, his one machine cycle=12/24M Second;
Instruction cycle
The time required to execute an instruction is generally composed of several machine cycles. Different commands require different machine cycles