catalogue

1, Introduction to Verdi

2, Verdi usage target

1. Generate fsdb waveform

    Three variables

    Three commands

    Two methods

    Three EDA manufacturers

2. Check fsdb waveform and track RTL code debug

1, Introduction to Verdi

      Verdi is a powerful debugging tool, which can be debugged with different simulation software. Many enterprises often use VCS+Verdi to simulate and check the code. Verdi is mainly used by IC Verification Engineer (Debug) and IC Design Engineer (Review).

2, Verdi usage target

There are three main steps to use Vverdi: generate fsdb waveform - view fsdb waveform - Track RTL code debug.

1. Generate fsdb waveform

    Three variables

• VERDI_HOME/NOVAS_HOME: the emulator defaults and prepares for setting PATH
•   PATH: let the system (Linux) find verdi
•   LD_LIBRARY_PATH: enable the system (Linux) to find the library files required by Verdi. So (static library),. A (dynamic library),. Tab (table file)

    Three commands

• Echo (with sed): query (print) environment variables. The pipeline command | is equivalent to giving the results on the left side of the pipeline to the commands on the right side for execution

        echo $PATH | sed ‘s/\:/\n/g’   ， Global replacement, replacing colon with newline character
        echo $LD_LIBRARY_PATH | sed 's/\:/\n/g'

• Which: query whether the current software is set. If the setting is successful, the software path will be displayed. Use which verdi
• uname -i: query the current system information. For example, the hardware platform 64bit is x86_ i386 for 64 / amd64,32bit platform     

    Two methods

• Use the Verilog system function and add the following code to the test code

      initial begin
         $fsdbDumpfile("top_tb.fsdb");
         $fsdbDumpvars(0,"tob_tb");
      end

• Use UCLI and TCL interfaces (VCS uses TCL script)

    global env
        fsdbDumpfile "$env(demo_fifo).fsdb"
        fsdbDumpvars 0 "top_tb"
    run

         Comparison of advantages and disadvantages of two main methods of Dump waveform

	Based on system function	Based on ucli/tcl interface
excellent	1. New employees are familiar with Verilog code and accept it quickly	1. There is no need to recompile the simulation top layer; 2. Using high-level language interface, it is easy to complete complex processing, such as transferring variables, such as using regular expressions; 3. Interactive interface, flexible control, and dump information can be modified in the simulation process, such as dumpon/dumpoff
lack	1. The system needs to be recompiled, which wastes time (when valueplusargs is not used); 2.Verilog is a low-level language, which is difficult for text processing and does not support regular expressions	1. Most new employees are not familiar with Tcl and accept it slowly

    Three EDA manufacturers

• Synopsys: VCS + Verdi
• Cadence : irun + Verdi
• Mentor : Questa + Verdi

Makefile script of VCS: those related to Verdi are annotation contents, using ucli interface

com:
    vcs -full64 \
    -sverilog \
    -debug_pp \                                             # Enable UCLI command
    -LDFLAGS \                                              # The linker that passes parameters to VCS is used in conjunction with the following three lines
    -rdynamic \                                             # Indicates the dynamic library to load, such as libsscore_vcs201209.so
    -P ${VERDI_HOME}/share/PLI/VCS/${PLATFORM}/novas.tab \  # Load table file
    ${VERDI_HOME}/share/PLI/VCS/${PLANTFORM}/pli.a \        # Load static library
    -f ../${demo_name}/tb_top.f \
    +vcs+lic+wait \
    -l compile.log

sim:
    ./simv \
    -ucli -i ../scripts/dump_fsdb_vcs.tcl \                 # ucli's input file (- i) is a tcl script
    +fsdb+autoflush \                                       # The command line parameter autoflush simulates and dumps the waveform at the same time. Without this parameter, the waveform will not be dumped. You need to type fsdbDumpflush after ucli command run 100ns to dump the waveform
    -l sim.log

 

   Where dump_fsdb_vcs.tcl (ucli script is Tcl language)

    global env                             # tcl script refers to environment variables, which are defined in Makefile through export   
    fsdbDumpfile "$env(demo_name).fsdb"    # Set the waveform file name, which is controlled by the environment variable env(demo_name)control   # demo_name uses export demo in makefile_ name=demo_ fifo  
    fsdbDumpvars 0 "tb_top"                # Set the top level and level of the waveform, indicating that TB will be used_ Top as the top level, Dump all levels
    run                                    # After setting the dump information and starting the simulation (at this time, the simulator is controlled by ucli), you can run 100ns and stop when simulating 100ns

 

    You can also use interactive simulation: note content can be typed during the simulation

global env
fsdbDumpfile "$env(demo_name).fsdb"
fsdbDumpvars 0 "top_tb"
run 200ns
#fsdbDumpoff
#run 100ns
#fsdbDumpon
#run

 

 

questa script:

compile:
    vlib work
    vmap work work
    vlog \
    -64 \
    -sv \
    +acc \                                                            # +acc make loading PLI valid
    -f ../${demo_name}/tb_top.f \
    -l com.log

run:
    vsim \
    -64 \
    -batch \
    -novopt \
    -pli ${VERDI_HOME}/share/PLI/MODELSIM/${PLATFORM}/novas_fli.so \  # Load shared objects
    work.tb_top \
    -do ../scripts/dump_fsdb_questa.tcl \
    +fsdb_autoflush \
    -l sim.log

 

    dump_fsdb_questa.tcl

gloal env 
fsdbDumpfile "$env(demo_name).fsdb"
fsdbDumpvars 0 "tb_top"
run -all
quit -sim

 

Requirements for dump waveforms in different scenarios

Write a picture description here

       2. Check fsdb waveform and track RTL code debug

For details on Verdi, see Verdi quick use tips_ yh13572438258 blog - CSDN blog
Reference link: https://blog.csdn.net/immeatea_aun/article/details/80961258