System Verilog learning notes - randomization constraint types

1. Why introduce randomization?

  1. With the increase of chip size and complexity, directional testing can not meet the needs of verification, while the proportion of random testing is gradually increasing
  2. Directional testing can find defects that you think may exist, while random testing can find defects that you don't even think of
  3. The environmental requirements of random testing are more complex than directional testing. It needs incentive, reference model and online comparison. Hundreds of simulations no longer need human participation, so as to improve the verification efficiency
  4. Compared with directional testing, random testing can reduce a considerable amount of code, and the generated incentives are more diverse than directional testing

2. What needs randomization test?

  1. Device configuration: through registers and system signals
  2. Environment configuration: randomize the verification environment, such as reasonable clock and external feedback signal
  3. Original input data: for example, the length and bandwidth of data packets, and the order between data
  4. Delay: the timing relationship between handshake signals, such as the timing relationship between valid and ready, req and ack
  5. Protocol exception: if the feedback signal gives an exception, can the design maintain the stability of subsequent data processing

3. Randomization method

The common randomization method is to use the keywords rand and randc to generate random sequences. The differences between the two are as follows:

//rand is ordinary random, and the value in each cycle can be repeated
class rand;
  rand bit[1:0] x;
// The results of random 5 times: 0 3 0 2 1, the probability of their occurrence is 1 / 4

//randc is periodic and random, and the values in each cycle are not repeated
class randc;
  randc bit[1:0] y;
// Results of random 5 times: 0 3 2 1 3. The probability of the first number 0 is 1 / 4. Since the values in each cycle are not repeated, the second number
 The probability of two values 3 is 1/3,The probability of the third value 2 is 1/2,The probability of the fourth value 1 is 1/1;Then enter the next step
 One cycle

4. Types of random constraints

4.1 Boolean expressions

Boolean expression is to use the simplest inequality to specify the value range of variables or the size relationship between variables

class order;
  rand bit[7:0] lo,med,hi;
  constraint bad//It is equivalent to lo < Med < Hi, but only one unequal sign can be recognized in sv at a time, so it should be written separately as follows

4.2 weight distributions

The weight distribution is to determine the probability of each value.

There are two expressions for weight allocation, namely: = and: /. Their usage and differences are as follows:

class wd;
  rand int src,dst;
  constraint c_dis
    src dist{0:=40,[1:3]:=60};//A:=B means that the weight of a is B, [1:3]: = 60 means that the weights of 1, 2 and 3 are 60 respectively
    /* src=0,weight=40/220
       Denominator 220 = 40 + 60 * 3      */

    dst dist{0:/40,[1:3]:/60};//A:/B means that the weight of a is B, [1:3]: / 60 means that the weights of 1, 2 and 3 are 60 / 3 = 20 respectively
    /* dst=0,weight=40/100
       Denominator 100 = 40 + 20 * 3      */

4.2. 1 weight distribution with variable

typedef enum {READ8,READ16,READ32} read_e;

class ReadCommands;
  rand read_e read_cmd;
  int read8_wt=1,read16_wt=1,read32_wt=1;//Weight value

  constraint c_read
    read_cmd dist
      READ8:=read8_wt,  //READ8 probability 1 / 3
      READ16:=read16_wt,//READ16 probability 1 / 3
      READ32:=read32_wt //READ32 probability 1 / 3
//By assigning the weight value to the variable, the weight value can be changed from outside the class through the variable

4.3 Range expressions

class RV;
  rang int c;
  int lo,hi;

//Specify the upper and lower limits of random values
  constraint c_range
    c inside{[lo,hi]};//lo<=c<=hi

//The upper and lower limits of random values are reversed
 constraint c_range
    !(c inside{[lo,hi]});//c<lo or c>hi

//$specify upper and lower limits
  rand bit[6:0]b;
  rand bit[5:0]e;

  constraint c_range
    b inside {[$:4],[20:&]};//0<=b<=4 or 20<=b<=127;$ On the left represents the minimum value, $on the right represents the maximum value
    e inside {[$:4],[20:&]};//0<=e<=4 or 20<=e<=63

//Use array
  rand bit[6:0]f;
  int fib[5]='{1,5,3,9,2};
  constraint c_range
    f inside fib;//The value of f is taken from the array fib


4.4 Conditional expressions

class stim;
  bit flag;
  rand bit[31:0] dst;

  constraint c_stim
    if(flag)//If flag=1, the dst range is 40-80
      dst inside {[40:80]};
    else//If flag= 1, then the dst range is 2-10 or 50-67
      dst inside {[2:10],[50,67]};

//Another way of writing
  constraint c_stim
    flag -> dst inside {[40:80]};
    !flag -> dst inside {[2:10],[50,67]};

4.5 external constraints

External constraint means that the constraint is not specified directly in the class, but is specified when used externally, as shown below:

class Packet;
  rand bit[7:0] length;
  rand bit[7:0] payload[];//Dynamic array

  constraint c_valid

  constraint c_external;//No constraints specified

program test;
  constraint Packet::c_external{length==1};//Note:

4.6 bidirectional restraint

Unlike top-down program code, constraint blocks are declarative code and executed in parallel. All constraint expressions are valid at the same time, so SV will calculate all random variable constraints at the same time and take their intersection.

class sx;
  rand logic [15:0] r,s,t;
  constraint c_bitir//Equivalent to 25 < s = = R < T < 30

Keywords: systemverilog

Added by TheNookie on Sat, 25 Dec 2021 05:13:23 +0200