System Verilog - Coverage
1, Coverage type
Code coverageassertion coverage Functional coverage
2, Function coverage strategy
If the function coverage is high but the code coverage is low, it indicates that the verification plan is incomplete and the test does not execute all the designed code.If the code rate is high but the function coverage is low, it means tha ...
Added by kev wood on Fri, 25 Feb 2022 06:22:26 +0200
sv_labs learning notes - sv_lab5_ Upper (System Verilog)
This section will introduce the first part of lab5, which mainly summarizes the ways of learning and thinking about general design and the points that need to be emphasized. At the same time, taking lab5 as a reference, it will analyze the flow direction of data flow, verify the communication and abstraction of components, and realize the overa ...
Added by ROCKINDANO on Fri, 07 Jan 2022 08:22:00 +0200
System Verilog learning notes - randomization constraint types
1. Why introduce randomization?
With the increase of chip size and complexity, directional testing can not meet the needs of verification, while the proportion of random testing is gradually increasingDirectional testing can find defects that you think may exist, while random testing can find defects that you don't even think ofThe environment ...
Added by TheNookie on Sat, 25 Dec 2021 05:13:23 +0200
SV casts and constants
1. Cast type
1.1 static conversion (compile time conversion)
There are three types of static conversion, namely data type coercion, vector width coercion and symbol coercion. The formats are:
Data type cast: '() 7 + int'(2.0 * 3.0); //Converts the result of (2.0 * 3.0) to an integer
//Then add 7
Vector width cast: '() logic [15:0] ...
Added by bobbythenewb on Mon, 13 Dec 2021 16:32:33 +0200