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Write in front         Connect to the slave interface, this paper continues to package the IP of an axi4 full master interface, learn the source code, and then simulate the waveform. Take you to a quick start AXI4 bus -- AXI4 full chapter (2) -- Xilinx AXI4 full interface IP source code simulation analysis (Slave interfac ...

1. What is FIFO          FIFO is a first in first out data buffer, which is widely used in logic design. FIFO design can be said to be a common sense design that logic designers must master. FIFO is generally used to isolate places where the read-write bandwidth on both sides is inconsistent or the bit w ...

1. What is SPI protocol          SPI (Serial Peripheral Interface) communication protocol is a synchronous serial interface technology proposed by Motorola Company. It is a high-speed, full-duplex, synchronous communication bus. Only four pins are used to control and transmit data in the chip. It is wide ...

1. Combination logic Combinational logic refers to the logic circuit whose output is only related to the current input logic level and has nothing to do with the original state of the circuit. It belongs to memoryless circuit and is commonly used in multiplexers, adders, decoders, etc 1.1 implementation of assignment stateme ...

When HDL is used to realize the frequency divider, it is mainly realized by writing the rising / falling edge of counter counting clock. Even frequency division is very easy to be realized here. Odd frequency division needs to generate two waveforms by counter and then perform exclusive or operation to ...

I. Preface FIFO is the most common and basic topic when applying for IC front-end related positions. FIFO is often used for data caching, bit width conversion, asynchronous clock domain processing. With the rapid growth of chip size, flexible system verilog has become the basic skill of designers and validators. Starting with the simplified ve ...

What is Async/Await?   async/await is a new way to write asynchronous code. Previous methods include callback functions and Proise. async/await is based on Promise, which can not be used for ordinary callback functions. Like Promise, async/await is non-blocking. async/await makes asynchronous code look like synchro ...

1. Introduction to PLI functions Verilog PLI(Programming Language Interface) is a mechanism for Verilog code to call C/C++ functions. It enables Verilog to call C/C++ functions written by users like some system calls (e.g. $display/$stop/$random), so that we can start our own system task/function with C/C++ language to realize the inconvenient ...

Target Reflected Echo Detection Algorithms and Their Implementation on FPGA Part 3: Top-level Implementation of Square and Integral Circuits and Algorithms Some time ago, I came into contact with a project of sonar target echo detection. The core function of sonar receiver is to recognize the echo of the excitation signal emitted by the transmi ...