Programming VIP

catalogue 1, Introduction to Ethernet communication 1.OSI seven layer model 2. Ethernet packet analysis 3.IP header checksum calculation and inspection 2, Ethernet communication example 1. Overall experimental block diagram 2. Sequence diagram of transmission part 3. Experimental code and simulation results summary 1, Introduction ...

I Basic characteristics of SDRAM 1. Internal memory bank-row-columnThere are four banks in total. Each bank has 213 rows and 29 columns, each of which is 16bit 2. Refresh cycle 8192refresh cycles/64ms, refresh one line every 7.8us on average 3. Introduction to data reading and writing and command sending SDRAM provides programmable read ...

preface This article starts with: https://www.ebaina.com/articles/140000010059 We use the generate statement in verilog to generate code blocks conditionally or iteratively in our design. This allows us to: Selectively include or exclude code blocks,Create multiple instantiations of a given code block. This is very important and convenient ...

RTL and integrated concept RTL (Register Transfer Level) refers to the HDL level of the circuit by describing the logic function from register to register without paying attention to the details of register and combinational logic (such as how many logic gates are used, the connection topology between logic gates, etc.). RTL level is a higher ...

Task - Verilog's task Previous articles recorded the use of functions such as function function: Function -- Verilog function . This time, record the function of using the task task task. a thing for it IIC save module needs to be used in the design, so there needs to be a corresponding master module in testbench, and a model that can read ...

Title: According to the basic principles of classroom teaching, I try to write an IIC control logic and FPGA output The input clock is 10MHz and the communication frequency of IIC is 400KHz. FPGA is required to write control to AD chip System instruction, the address of AD chip is 0000123 (changed to decimal 123, i.e. 01111111), AD chip ...

4.3 verify the implementation effect of OpenMIPS 4.3.1 implementation of instruction memory ROM In this section, we verify whether OpenMIPS is implemented correctly, including whether the pipeline and ori instructions are implemented correctly. The instruction memory ROM is read-only, and the interface is shown in the figure: `include "defin ...

preface    in the last course, we learned about nixie tube and realized the static display of nixie tube through code. This course will continue the content of the previous lesson and explain the dynamic display of nixie tube.   tip: I learned about nixie tube last class, so I skipped the explanation of nixie tube and b ...

preface The previous article introduced various electrical standards related to the serial port. The last article mainly introduced how to use Verilog language to complete the serial port receiving function. This article mainly introduced how to complete the serial port sending function, and included a flexible check bit design. In the p ...

preface   in the previous course, we learned led light control, key anti chattering, key control buzzer and so on. This paper will introduce the state machine. Based on the previous courses, the state machine will be used to design the water lamp and simulate the electronic door lock. 1, Introduction to finite state machine &ems ...