Write in front
Connect to the slave interface, this paper continues to package the IP of an axi4 full master interface, learn the source code, and then simulate the waveform.
Take you to a quick start AXI4 bus -- AXI4 full chapter (2) -- Xilinx AXI4 full interface IP source code simulation analysis (Slave interfac ...
Added by truck7758 on Mon, 29 Nov 2021 23:06:37 +0200
1, Principle of nixie tube dynamic display
In fact, the dynamic display of nixie tube is an upgraded version of the static display of nixie tube. The segment selection signal given is the same, that is, which word is displayed, but the difference depends on which bit selection signal is given, that is, which nixie tube is displayed. Give ...
Added by microbluechip on Mon, 29 Nov 2021 16:46:04 +0200
Written by @hzj
1. Fixed point positioning of filter and use of Beyond compare
(1) Why fixed-point positioning?
1. Fixed point: the existence of fixed point is due to the binary operation inside FPGA. The decimal point (floating-point data) in the actual operation cannot be accurately represented by bi ...
Added by mosherben on Mon, 22 Nov 2021 23:47:16 +0200
1 DDS principle
1.1 interpretation in the book
DDS (Direct Digital Synthesizer) technology is a new frequency synthesis method. It is a frequency synthesis technology that directly synthesizes the required waveform from the phase concept. It directly generates various signals of different frequencies and different waveforms by controlling ...
Added by canishk on Sat, 06 Nov 2021 18:02:08 +0200
1. What is FIFO
FIFO is a first in first out data buffer, which is widely used in logic design. FIFO design can be said to be a common sense design that logic designers must master. FIFO is generally used to isolate places where the read-write bandwidth on both sides is inconsistent or the bit w ...
Added by Plagel on Thu, 04 Nov 2021 05:10:01 +0200
1. What is SPI protocol
SPI (Serial Peripheral Interface) communication protocol is a synchronous serial interface technology proposed by Motorola Company. It is a high-speed, full-duplex, synchronous communication bus. Only four pins are used to control and transmit data in the chip. It is wide ...
Added by new_programmer on Tue, 26 Oct 2021 20:31:28 +0300
Device: Xilinx zynq 7035 Version: vivado2019.2 Implementation: 10.1376G serdes, a 6664B coded 4-Pair serdes routine with 64bit input and 64bit output, and the reference clock is 153.6MHz Objective: to record the process from simulation to on-board debugging for easy recall
Detailed settings of IP core
First tab GT Selection Second tab GT ...
Added by kitchin on Sat, 16 Oct 2021 20:38:02 +0300