Programming VIP

1, Introduction to VGA and AN430 1.VGA VGA(Video Graphics Array) is a video transmission standard launched by IBM with PS/2 machine in 1987. At that time, it had the advantages of high resolution, fast display speed and rich colors, and was widely used in the field of color display. VGA interface is the interface that outputs analog signa ...

1, Preliminary preparation SoC learning chapter - realizing hello FPGA printing Prepare the hardware that should be ready 2, Add PIO peripherals 1, Gold reference project 1. Open the gold reference project 2. Open Platform Designer 3. Open the corresponding qsys file 4. Add PIO_LED and PIO_KEY nameBit widthInput and outputPIO_ ...

RTL and integrated concept RTL (Register Transfer Level) refers to the HDL level of the circuit by describing the logic function from register to register without paying attention to the details of register and combinational logic (such as how many logic gates are used, the connection topology between logic gates, etc.). RTL level is a higher ...

Topic 1. Differences between bit, byte, word, DWORD and qword 1byte = 8bit 1word = 2byte = 16bit 1dword = 2word = 4byte = 32bit 1qword = 2dword = 4word = 8byte = 64bit Topic 2. What is the original code, inverse code, complement code, symbol value code. Taking 8bit as an example, the numerical ranges of their respective representati ...

Task - Verilog's task Previous articles recorded the use of functions such as function function: Function -- Verilog function . This time, record the function of using the task task task. a thing for it IIC save module needs to be used in the design, so there needs to be a corresponding master module in testbench, and a model that can read ...

preface    in the last course, we learned about nixie tube and realized the static display of nixie tube through code. This course will continue the content of the previous lesson and explain the dynamic display of nixie tube.   tip: I learned about nixie tube last class, so I skipped the explanation of nixie tube and b ...

Introduction to MIG IP core In Xilinx series FPGA, in order to facilitate users to read and write DDR, the official provides an IP core MIG for accessing DDR, which is fully called Memory Interface Generator. For details, please refer to the official Xilinx document reference manual: ug586(7 Series Devices Memory Interface Solutions v4.1). The ...

preface The previous article introduced various electrical standards related to the serial port. The last article mainly introduced how to use Verilog language to complete the serial port receiving function. This article mainly introduced how to complete the serial port sending function, and included a flexible check bit design. In the p ...

preface   in the previous course, we learned led light control, key anti chattering, key control buzzer and so on. This paper will introduce the state machine. Based on the previous courses, the state machine will be used to design the water lamp and simulate the electronic door lock. 1, Introduction to finite state machine &ems ...

Write in front         Connect to the slave interface, this paper continues to package the IP of an axi4 full master interface, learn the source code, and then simulate the waveform. Take you to a quick start AXI4 bus -- AXI4 full chapter (2) -- Xilinx AXI4 full interface IP source code simulation analysis (Slave interfac ...