FPGA notes summary (open...)

1. Combination logic Combinational logic refers to the logic circuit whose output is only related to the current input logic level and has nothing to do with the original state of the circuit. It belongs to memoryless circuit and is commonly used in multiplexers, adders, decoders, etc 1.1 implementation of assignment stateme ...

Added by thefortrees on Fri, 22 Nov 2019 21:31:41 +0200

VHDL/Verilog HDL implementation of arbitrary integer multiplexer

When HDL is used to realize the frequency divider, it is mainly realized by writing the rising / falling edge of counter counting clock. Even frequency division is very easy to be realized here. Odd frequency division needs to generate two waveforms by counter and then perform exclusive or operation to ...

Added by phpQuestioner_v5.0 on Sat, 19 Oct 2019 19:34:41 +0300

Synchronized FIFO design and IP level verification

I. Preface FIFO is the most common and basic topic when applying for IC front-end related positions. FIFO is often used for data caching, bit width conversion, asynchronous clock domain processing. With the rapid growth of chip size, flexible system verilog has become the basic skill of designers and validators. Starting with the simplified ve ...

Added by ianhull on Sat, 21 Sep 2019 15:43:49 +0300

The difference between promise and async and await

What is Async/Await?   async/await is a new way to write asynchronous code. Previous methods include callback functions and Proise. async/await is based on Promise, which can not be used for ordinary callback functions. Like Promise, async/await is non-blocking. async/await makes asynchronous code look like synchro ...

Added by koughman on Fri, 26 Jul 2019 10:46:29 +0300

Introduction of Verilog PLI and Three Methods of Running NC

1. Introduction to PLI functions Verilog PLI(Programming Language Interface) is a mechanism for Verilog code to call C/C++ functions. It enables Verilog to call C/C++ functions written by users like some system calls (e.g. $display/$stop/$random), so that we can start our own system task/function with C/C++ language to realize the inconvenient ...

Added by benutne on Wed, 05 Jun 2019 21:45:05 +0300

Target Reflected Echo Detection Algorithms and Their Implementation on FPGA Part 3: Top-level Implementation of Square, Integral Circuits and Algorithms

Target Reflected Echo Detection Algorithms and Their Implementation on FPGA Part 3: Top-level Implementation of Square and Integral Circuits and Algorithms Some time ago, I came into contact with a project of sonar target echo detection. The core function of sonar receiver is to recognize the echo of the excitation signal emitted by the transmi ...

Added by headcutter on Sat, 18 May 2019 14:58:01 +0300